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1/3 january 2002 AN1174 application note use the psd813f to minimize signal conditioning system hardware contents (introduction on next page)
1 use the psd813f to minimize signal conditioning system hardware by: don buccini introduction the proliferation of inexpensive microcontrollers, dsps and memory has fueled an explosive growth in hardware and systems that monitor and interface with the physical world. this physical world, which is perceived through the human senses, is analog in nature and must be converted into a format that is compatible with today?s data acquisition technology. specific sensors are designed to monitor this physical stimulus. the accelerating growth in markets such as environmental, process controls, automotive, hvac, appliances, etc., is forecasted to grow the sensor market from $10.4 billion in 1995 to $20.1 billion in 2000. the data received from these sensors is conditioned and processed by microcontrollers and dsps for subsequent data sampling, processing, and storage. purpose this application note focuses on the signal conditioning marketplace and how the flash-based psd813f family greatly simplifies the hardware design effort while adding enhanced features such as concurrent memory and in-system-programming for easy remote field upgrades. familiarity with the psd813f is assumed. please reference psd813f data sheet for a detailed description of the device. the design example will use the analog devices aduc812 multi-channel 12-bit adc with embedded 8051 mcu core. this is a highly integrated device with 8 analog inputs and 12-bit adc accuracy, allowing a 3-chip design solution, including the psd813f, and external sram for data storage. signal conditioning overview figure 1 is a block diagram showing the hardware components of a typical signal conditioning system. the individual components perform the following functions: sensor/transducer a sensor is a device that monitors physical stimulus such as temperature, pressure, acceleration, etc. and converts it into a measurable output signal. a transducer is the circuitry associated with the specific sensor that creates the voltage or current excitation for further processing by the signal conditioner. this signal can be a variable voltage level, a pulse or periodic waveform, or other measurable formats.
2 figure 1. block diagram C typical signal conditioning system analog waveform pcm pcm data bus signal conditioner the signal conditioner optimizes the output voltage from the transducer to match the input range of the analog-to-digital converter (adc). the most frequent form of signal conditioning is amplification of low level output signals. the signal conditioner also receives digital data from the microcontroller/pc and converts it to an analog signal to drive analog meters, chart recorders and other analog instrumentation. analog multiplexer and adc this analog-to digital converter converts multiple analog sensor inputs, which are switched in sequence to the adc, to an n-bit digital value. the sampling rate (frequency response) is dependent on the maximum clock rate of the adc. this digital value is transferred to the microcontroller or pc for processing, displaying and storage. microcontroller in addition to processing, displaying and storing the sampled data, the microcontroller performs a variety of other functions - i/o, controlling the signal conditioning component, chip selects for external peripherals, keyboard scan, etc. digital-to analog converter (dac) the data which is processed in digital format can be reformatted through the digital-to analog converter to generate a signal which can be used to drive analog instrumentation such as panel meters and chart recorders and graphs. figure 2 is a block diagram illustrating how the psd813f and aduc812 reduce all of the hardware components of the signal conditioning system in figure 1 (except the sensors and analog instruments) to three ics. signal conditioner multiplexed input channels micro- controller or dsp sensors / transducers n-channel analog mux and n-bits adc program mem o ry data s t o ra g e i/o analog i ns tr u me n t s dac
3 analog instruments smart sensors figure 2. block diagram C minimized signal conditioning system hardware pa a0-a7 a0-a7 o0-o7 d0-d7 p0 ad0-ad7 adio[7:0] p2 a8-a23 adio[15:8] a16 a8-a15 a8-a15 aduc812 pb a16 p3 psd813f i/o ce1 pc sram p1 pd 128k x 8 i/o jtag
4 psd813f1 architecture figure 3 is a block diagram of the psd813f1 that contains all of the options available in the psd813f family. table 1. shows the function matrix of the family. the differences are in the memory options available on each part. the on-chip features supply many of the key elements to implement an effective two-chip signal conditioning system, depending on system requirements. the on-chip 32 kbytes of byte-erasable flash eeprom may possibly be used in place of external sram. these features include: * an easily programmable bus interface to the microcontroller with external 8-bit boot code and/or program code capability. * 128 kbytes of main flash memory, divided into eight equal individually protected sectors. * separate 32 kbytes eeprom or flash boot memory divided into four equal blocks. * concurrent programming of the flash or eeprom/boot flash memories allows execution from one memory while reprogramming the other. * 2 kbytes scratchpad sram (8 kbytes in future pin-compatible upgrade). * two flash-based plds with 16 output micro cells and 24 input micro cells. * 27 individually configurable i/o port pins. each may be defined as mcu i/os, pld i/os, latched mcu address outputs or special function i/os. * 8-bit page register to expand the address space by a factor of 256. * jtag compliant serial port for true in-system programming (isp) of blank devices or reprogramming of devices in the factory or field. table 1. psd813f product matrix device flash main memory kbit (8 sectors) additional memory for boot and/or data (4 sectors) sram kbit psd813f1 1024 256 kbit eeprom 16 psd813f2 1024 256 kbit flash 16 psd813f3 1024 none 16 psd813f4 1024 256 kbit flash none psd813f5 1024 none none for this application, the psd813f5 is used. the 8 kbytes of flash memory in the aduc812 will be used for both boot and program code, and the 1024 kbytes flash memory in the psd813f5 will be used for extended program code.
5 development systems the psd family is supported by the st windows 95 & 98 and nt-based software development system, psdsoft. this software contains several elements to simplify the design task. the pld design entry uses an hdl-psdabel, which creates a minimized logic implementation, and provides logic simulation of the plds. the 8051 bus interface is defined in psd bus configuration. the psdcompiler, comprised of a fitter and address translator, generates an object file from the psdabel, psdconfiguration and mcu firmware files. the object file is then downloaded to a programmer (st psdpro, st flashlink, data i/o or other third party programmers for device programming) or to psdsimulator for device-level simulation. figure 3. psd813f1 block diagram pd0 pd1 pd2 i/o port pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 i/o port pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 i/o port pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 i/o port ad0 mcu addr/ data ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 mcu control cntl0 cntl1 cntl2 (pd 0) power mangmnt apd / turbo complex pld 24 input micro<>cells 16 output micro<>cells a b a b a b a b a b a b a b a b b c b c b c b c b c b c b c b c page reg runtime control csiop reg file security lock pld input bus allo- cator flash 8 blocks, 16 kb 128 kbytes total pin feedback ecs (3) periph i/o mode rs0 ees0-3 csiop node feedback psd813f1 internal addr, data, control bus linked to mcu decode pld and array sram 2kbyte - batt b/u eeprom 4 blocks, 8 kb 32 kbytes total external chip selects fs0-7 jtag-isc tap controller oe oe oe vm reg vstby aaaaaaaa bbb bbbbb c c c c c c c c rst\ to pld in bus
6 st offers two low-cost device programmers: psdpro ....plugs into a pc/laptop parallel port and is a replacement for the st magicpro iii. flashlink ....is a low cost cable that plugs into a pc/laptop parallel port to support jtag programming. flashlink is controlled by psdsoft and supports device chaining of multiple psds and devices from other manufacturers. programming the psd813f in-circuit using the jtag interface port c shares its i/o pins with the jtag interface. this allows maximum utilization of port c i/o lines if the mutiplexed option is selected, since port c is freed up for i/o functions once the jtag operation is complete. the psd813f configuration, pld logic, flash memory and eeprom can be programmed through this interface. the standard jtag signals are tms, tck, tdi, and tdo. tstat and /terr are jtag extensions that can be used to speed up programming the psd813f. for a detailed description of the st jtag interface specification, please reference application note 054 jtag information C psd813f. interfacing the psd813f to the aduc812 psd813f bus interface the psd813f has a user-friendly programmable bus interface that is quickly configured to interface directly to most microcontrollers and general purpose dsps with no glue logic. table 2 lists the bus interface signals from the aduc812 used to access the flash memory, eeprom, sram and pld logic inside the psd813f.
7 table 2. bus interface pin functions aduc812 pin functions psd813f pin functions pin description p0.0 C p0.7 (a/d0 C a/d7) adio0 C adio7 multiplexed low-order address/data bus accesses external program or data memory p2.0 C p2.7 (a8 C a15) adio8 C adio15 high-order address byte when accessing external 64 kbytes program memory space p2.0 C p2.1 (a16 C a17) pb0 C pb1 high-order address byte when accessing external 16 mbytes data memory space pb0 & pb1 latch a16 & a17 during data access p3.6 - /wr cntl0 active low write control pulse latches the data byte from port 0 into the external data memory p3.7 - /rd cntl1 active low read control pulse enables the external data memory to port 0 /psen cntl2 - /psen active low program store enable pulse enables the external program memory during instruction fetch ale pd0 - ale active high address latch enable pulse latches a0-a7 during external program memory fetch, and a0-a7 & a16-a23 during external data memory access bus interface timing calculation the aduc812 has a unique way of accessing external memory. psen is used to access 64 kbytes of external program memory, identical to the way the 8051 core microcontroller fetches external program code. the difference is in how the aduc812 accesses 16 mbytes of external data memory. during an external data access, port p2.0-p2.7 multiplexes a8-a15 with a16- a23. ad0-ad7 from port p0.0-p0.7 and a16-a23 are latched by ale. a8-a15 are unlatched outputs from p2.0-p2.7 which are stable when data is present on p0.0-p0.6, similar to the 8051 external memory fetch operation. figure 4. is the timing diagram for external data read/write access. aduc812 memory map the aduc812 has two separate 8-bit external address spaces C 64k program and 16m data. when ea=1, the first 8 kbytes of program code are executed from the internal 8 kbytes flash eeprom ; above 8 kbytes, program code is executed from external program memory. when ea=0, all 64kbytes of code are executed from external memory. the memory map is illustrated in figure 5, along with their respective select signals. address lines a23-a16 are multiplexed with a15-a8 to achieve the 16 mbytes data address range without using bank switching. ea is tied high to vcc for the system example in this application note.
8 figure 4. aduc812 external data memory read/write timing ale 127 min psen port 2 a16 C a23 a8 C a15 t lldv = 517 max t llwl = 300 max t rlrh =400 max rd t avll = 43 t llax = 48 t rhdz = 97 max port 0 a0 Ca7 data in (read) t avwl = 203 min t avdv = 585 max t llwl = 200 min t wlwh = 400 min wr t qvwh = 433 min t whqh = 33 min port 0 a0 C a7 data out (write)
9 figure 5. aduc812 program and data memory map program memory space data memory space read only read / write ffff ffffff psen = 0 rd = 0 2000 or wr = 0 0000 000000 ea = 1 ea = 0 interfacing to the aduc812 external memory bus the block diagram of figure 6 illustrates the bus interface between aduc812 and psd813f5. the aduc812 has 24 address lines and an 8-bit data bus to access external memory. when accessing external data memory, the aduc812 outputs a0-a7 and a16-a23 simultaneously to be latched by ale, before data is output on port 0. the psd813f5 latches a0-a7 on the dedicated ad0-ad7 pins. for this example, the psd813f5 uses two psd port b i/o pins and two internal input micro cells to latch a16 and a17 with ale; these latched address lines are brought out to two additional pins of port b. this allows up to 256 kbytes of external data sram, i/o and peripheral address locations to be accessed. the remaining external memory select signals are defined in psdabel design entry. figure 6. block diagram C aduc812 / psd813f5 bus interface p0 ad0 Cad7 adio[7:0] pa a0 Ca7 a8-a23 a8-a15 adio[15:8] a16 C a17 p2 pb /wr cntl0 - /wr la16-la17 /rd cntl1 - /rd p3 ale pd0 C ale pc i/o /psen cntl2 - /psen pd i/o aduc812 psd813f5 external program memory space internal 8 kbytes flash eeprom external program memory external data memory space
10 figure 6 shows how latching a16 and a17 is implemented in the psd813f5 pld. figure 6. latching a16 and a17 in the psd813f5 cpld input i/o port b micro cell 0 a16 a15 C a0 a17 ale la16 la17 sram_cs in put micro cell figure 7 is the schematic diagram of the aduc812 / psd813f interface. the 128 kbytes sram is used for data storage, but external data can be expanded to the full 16 mbytes by using an external 8-bit latch to latch a16-a23, freeing up the i/o pins of the psd813f for other functions. an alternative would be to use the 32 kbytes eeprom in the psd813f1, if this storage capacity and write speed is sufficient, and eliminate the external sram. define the aduc812 bus interface in psdsoft device configuration figure 8 is the mcu bus configuration screen imported from psdsoft device configuration utility. the bus interface between the aduc812 and psd813f is quickly configured by selecting the appropriate signals in this screen. the following bus signals are selected in the mcu bus configuration screen in psdsoft. a16 and a17 are connected to the cpld i/o pins and are included in the internal equations generated by psdabel design entry. * data bus width: 8-bit * address / data mode: mux * control setting: /wr, /rd, /psen * address latch / strobe setup: ale = active high * vm register configuration: flash = program space 0 1 2 3 4 q d g q d g and array
11 figure 7. schematic diagram C aduc812 to psd813f5 interface vcc vcc vcc d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a16 a17 la16 la17 /sram-cs u2 psd8 13 f 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pco/tms pc1/tck vstby pc 3/tstat pc4/terr pc5/tdi pc6/tdo pc7/bhe cntl0-r/w,wr cntl1-e,rd,ds cntl2-psen pd0-as-ale pd1-clkin pd2-csi reset u? km681000 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 24 29 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 cs1 cs2 oe we d1 d2 d3 d4 d5 d6 d7 d8 u1 a duc812 43 44 45 46 49 50 51 52 28 29 30 31 36 37 38 39 15 32 33 26 1 2 3 4 11 12 13 14 53 25 41 42 16 17 18 19 22 23 9 10 27 40 p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p2.0/a8/a16 p2.1/a9/a17 p2.2/a10/a18 p2.3/a11/a19 p2.4/a12/a20 p2.5/a13/a21 p2.6/a14/a22 p2.7/a15/a23 reset xta l1 xta l2 sclock p1.0/adc0/t2 p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 p1.4/adc4 p1.5/adc5/ss p1.6/adc6 p1.7/adc7 p3.6/w r p3.7/rd psen ale p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1/miso p3.4/t0 p3.5/t1/convst dac0 dac1 sdata/mos1 ea 1 2 3 4 analog instruments smart sensors r1 1k sw1 y1 sw1 is used for for the a duc812 flash eeprom serial dow nload protocol 100k jta g conn.
13 figure 8. psdsoft bus configuration define the psd813f5 decoding functions in psdabel design entry figure 9 is the example system memory whose program, data and i/o addresses are defined in the psdabel design entry screen. the psd813f5 page register is used to extend the external program address range of the 8031 beyond its 64k limitation. since paging is used, an area in memory containing routines common to all program memory pages C initialization, i/o and sram access, page switching, device drivers, etc. - must be accessible independent of which page the mcu is executing code from. to simplify setting up the system memory map within the 64k program address range of the aduc812 C that is, external flash memory starting at address location 200h, the upper 8 kbytes of sectors 3 and 7 in the psd813f5 flash memory are not used. the boot program and common program code is stored in the internal 8 kbytes flash eeprom in the aduc812 and is directly accessible from both page 0 and 1. when the program counter in the aduc812 is greater than 1fffh, code is fetched from the external psd flash memory in page 0 or 1.
14 figure 9. psd813f5/aduc812 system memory map with paging external external program memory data memory ffff 3ffff 20200 20000 2000 0000 00000 ea = 1 aduc812 flash eeprom serial download protocol the aduc812 accomplishes in-system-programming of code through the uart serial port (alternative to jtag). this download is entered automatically by resetting the chip while psen is pulled low through a 1k resistor. once the handshaking is completed and the entire hex file has been transmitted, control is reverted back to the internal eeprom flash by releasing the ground on psen and resetting the aduc812. this is illustrated in figure 10. figure 10. timing diagram - aduc812 serial download protocol psen reset using the psd813f concurrent memory feature (please reference figure 11). typically, it is very difficult to implement in-system- programming with a design using the 8031 architecture because of its separate program and data address spaces. the flash program memory must be temporarily placed in data space while the boot memory is placed in program space to execute minimum code to upgrade the flash memory. for this example, the boot resides in fixed common eeprom program memory space at address 0000h-1fff; the flash memory is placed in data space and temporarily overlaps the external sram data space at address 2000h-ffffh by setting the data bit (page register bit 7) to 1, disabling the external chip select signal (sram_cs) to the sram. the data bit is internal 8 kbytes flash eeprom boot & common code future expansion i/o & peripherals 128 kbytes sram page 0 page 1 64 kbytes 64 kbytes flash flash
15 configured in the psdabel design entry screen. figure 11 shows how program and data memory spaces are temporarily swapped during in-system-programming of flash memory. figure 11. memory swapping - program and data space program memory data program memory data page 0 page 1 memory memory ffff ffff sector sector 3 7 e000 sector sector 2 6 ext. flash a000 sector sector sram page 0 1 5 or 6000 sector sector page 1 0 4 2000 2000 aduc812 aduc812 flash eeprom flash eeprom boot and boot and common code common code 0000 0000 vm = 04h vm = 10h data = 0 data = 1 the psd813f5 easily accomplishes memory swapping using its concurrent memory features: 1. volatile memory (vm) register is used exclusively for 8031-core designs and controls whether program or data memory space is accessed by psen and rd. figure 12 shows the contents of the vm register at reset and when program and data spaces are swapped during the in-system programming (isp) operation. reset (reference figure 8). the psdsoft bus configuration screen is used to initially place flash memory in program space after reset. all memory accesses above 1fffh will fetch code from the psd813f5 flash memory. the bus configuration screen also configures the vm register to be set to 04h at reset, enabling psen to read flash memory while disabling read. in-system-programming setting the vm register to10h enables read and write to access flash memory and disables psen. reset & code execution (no rmal o perati on) psd flash memory update
16 2. page register any of the bits in the 8-bit page register which are not used to set up flash memory pages can be used as control bits for such functions as swapping program and data memory spaces and disabling chip selects to overlapping memory addresses during in- system programming. the procedure to update code in the psd813f5 flash memory by isp is straightforward: 1. the data bit (page register bit 7) is set to disable the sram_cs chip enable signal to the external sram; this allows flash memory to temporarily overlap the sram in data space. 2. set the vm register to 10h; this places flash program memory in data space by enabling the rd and wr signals from the 8031-core to access the flash memory. program code can now be downloaded via the uart serial port. 3. when isp code download is complete, the data bit is reset and the vm register is reset back to 04h, restoring code and data back to their respective memory spaces. figure 12. vm register codes for memory swapping example function/ hexcode bit 7 pio_en bit 6 not used bit 5 not used bit 4 fl_data bit 3 ee_data bit 2 fl_code bit 1 ee_code bit 0 sram _code system reset (04h) 000 0 = rd cant access flash 0 1 = psen can access flash 00 flash update (10h) 000 1 = rd can access flash 0 0 = psen cant access flash 00 summary the psd813f has universal applications across all markets. of no less importance is the rapidly growing signal conditioning market. the highly integrated psd813f, with the inclusion of previously difficult functions to implement C flash plds, concurrent memory and isp C allows the design engineer to add enhanced features to existing and new products with little or no additional cost. appendix the appendix contains the psdabel listing showing how the psd813f5 is configured to implement the example in this application note.
17 module aduc812 title 'minimal signal conditioning system using the psd813f5 and the analog devices aduc812'; "**** by: don buccini "**** date 3/19/99 "pin declarations "*********** mcu bus interface signal declarations ****************** "**** the following are 8031 bus input signals to the psd plds. wr pin; "cntl0 input:(pin 47)- write strobe rd pin; "cntl1 input:(pin 50)- read strobe psen pin; "cntl2 input:(pin 49)- program store enable ale pin; "pd0 input:(pin 10)- address latch enable reset pin; "input:(pin 48)- system reset a15..a0 pin; "input:(pins 46..39,37..30)- demuxed address "**** in addition to making these declarations, use the psd "**** configuration utility and make these selections: "**** * 8-bit muxed data bus "**** * /wr, /rd, /psen for control setting "**** * active high level for ale/as "**** * enable csi if used in application "**** * set the vm register. "******** port a, b, c, d pin declaration **************************** "**** port a pin assignments "**** port a is used to latch the low-order address bits. la0 pin; "i/o (pin 29)- port a pin pa0 la1 pin; "i/o (pin 28)- port a pin pa1 la2 pin; "i/o (pin 27)- port a pin pa2 la3 pin; "i/o (pin 25)- port a pin pa3 la4 pin; "i/o (pin 24)- port a pin pa4 la5 pin; "i/o (pin 23)- port a pin pa5 la6 pin; "i/o (pin 22)- port a pin pa6 la7 pin; "i/o (pin 21)- port a pin pa7 "**** port b pin assignments a16 pin 7 istype 'reg'; "port b pin pb0 a17 pin 6 istype 'reg'; "port b pin pb1 la16 pin 5; "port b pin pb2 la17 pin 4; "port b pin pb3 sram_cs pin 3; "port b pin pb4 pb5 pin; "i/o (pin 2)- port b pin pb5 pb6 pin; "i/o (pin 52)- port b pin pb6 pb7 pin; "i/o (pin 51)- port b pin pb7
18 "**** port c pin assignments "**** port c pins can be used for i/o and/ors pecial functions "**** such as the ieee 1149.1 jtag interface. pc0 pin; "i/o (pin 20)- port c pin pc0, or jtag tms pc1 pin; "i/o (pin 19)- port c pin pc1, or jtag tck pc2 pin; "i/o (pin 18)- port c pin pc2, or vstby pc3 pin; "i/o (pin 17)- port c pin pc3, or jtag tstat, or stdby on pc4 pin; "i/o (pin 14)- port c pin pc4, or jtag terr\, or rdy/busy pc5 pin; "i/o (pin 13)- port c pin pc5, or jtag tdi pc6 pin; "i/o (pin 12)- port c pin pc6, or jtag tdo pc7 pin; "i/o (pin 11)- port c pin pc7 "**** port d pin assignments "pd0 (pin 10) is assigned above as the ale signal from the "microcontroller and is not available for use as general i/o. //clkin pin; "port d pin pd1 (pin 9) can be used as a common "clock (clkin) to the plds and the power down "circuitry. if not used as a common clock, this "pin may be used as general i/o. //pd2 pin; "port d pin pd2 (pin 8) can be used as general i/o "or the global psd chip select (csi). if csi is "desired, do not declare the pin, go to the psd "configuration utility and enable csi. "******** dpld outputs and other internal node declaration ******** "**** main flash memory segments ************************ fs7..fs0 node; "this declaration is supported by all psd8xx devices "**** psd control registers ***************************** csiop node; "this declaration is needed for all psd8xx devices. "**** internal psd page register bits pgr0 node; "this one-bit page register is used to divide the psd813f5 "flash memory into two pages. "**** important. if page register bits are not used as address "**** extension bits (such as pgr0, pgr1, etc), but are "**** used to manipulate access of memory, then they should be "**** declared as individual page bit node numbers to be "**** compatible with the future mapping feature of psdsoft. here **** are the node numbers associated with page register bits. "**** "**** page register bit internal node number "**** pgr7 node 117 "**** pgr6 node 116 "**** pgr5 node 115 "**** pgr4 node 114 "**** pgr3 node 113 "**** pgr2 node 112 "**** pgr1 node 111
19 "**** pgr0 node 110 data node 117; " this page register bit (pgr7) will be used to " disable the external sram cs while the psd813f5 " flash memory is switched to the 80c31 data space "(rd and /wr are used to update flash memory through "the 80c31 uart. "**** jtag port select ********************************* jtagsel node; "used to select the jtag port active with a product term "******************************************************************* "definitions x = .x.; "don't care symbol page = [pgr0]; "you can use up to eight bits for memory paging. "here, only one bit is used to define two memory pages. address = [a17,a16,a15..a0]; "de-muxed microcontroller address signals laddr = [a17,a16]; equations "******** dpld equations ***************************************** "**** generate active high chip selects for the main flash segments. "**** each segment is 16k bytes for the psd813fx devices. "**** all psd8xx devices support fs7..fs0. fs0 = (address >= ^h2000) & (address <= ^h5fff) & (page == 0); fs1 = (address >= ^h6000) & (address <= ^h9fff) & (page == 0); fs2 = (address >= ^ha000) & (address <= ^hdfff) & (page == 0); fs3 = (address >= ^he000) & (address <= ^hffff) & (page == 0); fs4 = (address >= ^h2000) & (address <= ^h5fff) & (page == 1); fs5 = (address >= ^h6000) & (address <= ^h9fff) & (page == 1); fs6 = (address >= ^ha000) & (address <= ^hdfff) & (page == 1); fs7 = (address >= ^he000) & (address <= ^hffff) & (page == 1); "**** generate active high chip select for the psd control registers. "**** 256 contiguous bytes must be decoded for all psd8xx devices. csiop = (address >= ^h20000) & (address <= ^h200ff) & (page == x); "******** gpld/ecspld equations **************************************** "**** active low chip select for an external 128k byte sram: !sram_cs = (address >= ^h00000) & (address <= ^h1ffff) & !data; laddr.ld = ale; la16 = a16; la17 = a17; end return to main menu
AN1174 - application note 2/3 table 1. document revision history date rev. description of revision sep-1999 1.0 document written (an060) in the wsi format 03-jan-2002 1.1 front page, and back two pages, in st format, added to the pdf file references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express
3/3 AN1174 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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